Overclocking the Infinity Fabric - The Corsair DDR4-5000 Vengeance LPX Review: Super-Binned, Super E

Posted by Martina Birk on Thursday, May 2, 2024

Infinity Fabric Overclocking: What the FCLK

With AMD’s 3rd generation Ryzen processors, AMD has increased the flexibility of the memory subsystem and added separate control for two elements dubbed FCLK and UCLK. These elements have technically always been present, but previously were always linked to memory speed. Before we proceed though, some definitions:

FCLK – Fabric ClocK. FCLK controls the speed of AMD’s Infinity Fabric, which handles communication across their CPUs. On 3rd generation Ryzen, Infinity Fabric and therefore FCLK or Fabric Clock has particular responsibility for the connections between the Core dies and the IO die. UCLK – Unified memory controller ClocK.

UCLK - This controls the speed of the memory controller itself.

MEMCLK – Memory clock on DDR4 memory is often referred to by the data rate, for example, this “5000 MT/s” kit is so called because at the advertised speed data is transferred 5000 million times per second. The physical clock signal that governs this data transfer, however, is 2500 MHz at the advertised speed – the data rate is double the physical clock, hence Double Data Rate. In AMD’s language this physical clock is called MEMCLK, and often shows up in bios settings under this name. MEMCLK is important because of how FCLK and UCLK relate to it.

Technically, all of these elements have always existed on all AMD’s Zen-based processors, back to 1st generation Ryzen and the enterprise equivalents, but FCLK and UCLK were always locked to MEMCLK making them effectively one and the same. What differs with 3rd generation Ryzen is that rather than being tied to MEMCLK, FCLK can now be set totally independently and UCLK has a choice of two ratios to MEMCLK – 1:1 and 1:2 (UCLK:MEMCLK).

Setting FCLK on Matisse

Although FCLK is now free to run at any speed, in practice there’s a performance bonus from running FCLK, UCLK and MEMCLK synchronized together. At lower MEMCLK speeds this may be outweighed by increasing – more specifically, overclocking – FCLK independently and when overclocking to very high MEMCLK it is simply no longer possible for FCLK to keep up and it must be run at a reduced speed.

By default FCLK, UCLK and MEMCLK are still synced together on 3rd generation Ryzen for speeds up to and including DDR4-3600 (1800 MHz FCLK/UCLK/MEMCLK), and as a result users with DDR4-3600 kits find these parameters well optimised without additional tweaking.

With this extremely high-speed DDR4-5000 kit, FCLK and UCLK cannot be synched with MEMCLK, and for the best possible performance, it’s advisable to manually overclock FCLK independently. On MSI motherboards as tested, the FCLK frequency and UCLK ratio (“UCLK DIV1 MODE”) are found in the “DRAM Setting” portion of the OC menu.

Test Bed

To test the performance of the Corsair Vengeance LPX DDR4-5000 memory kit, we tested the kit at three different frequencies with Infinity Fabric clocks in a ration of 2:1. Our maximum limit on the Infinity Fabric before we reached instability was 1800 MHz, which is a common limit for users. Some Ryzen 3000 processors can clock as high as 1900 MHz which would equal DDR4-3800, but AMD themselves say the sweet spot for memory performance on Ryzen 3000 and X570 is around DDR4-3600.

Test Setup
ProcessorAMD Ryzen 3700X, 65W, $329 
8 Cores, 16 Threads, 3.6 GHz (4.4 GHz Turbo)
MotherboardMSI MEG X570 Ace (BIOS 1.40 - ABBA)
CoolingID-Cooling Auraflow Pink 240mm AIO
Power SupplyThermaltake Toughpower Grand 1200W Gold PSU
Memory2x8GB Corsair Vengeance

Tested at:

DDR4-3200 18-26-26-46 1T (FCLK 1600 MHz)
DDR4-3600 18-26-26-46 1T (FCLK 1800 MHz)
DDR4-5000 18-26-26-46 1T (FCLK 1800 MHz)

Video CardASRock RX 5700 XT Taichi X 8G OC+ (1810/2025 Boost)
Hard DriveCrucial MX300 1TB
CaseOpen Benchtable BC1.1 (Silver)
Operating SystemWindows 10 1903 inc. Spectre/Meltdown Patches

ncG1vNJzZmivp6x7orrAp5utnZOde6S7zGiqoaenZH52fJdyZq2glWKwsL7SmqCrZZSZv3V5lGlnaWWmmruoscCnmp5lnKXFbrnEpqarsV2nsre1xLBmaw%3D%3D